1. Field of the Invention
The present invention relates to a diagnostic circuit, and more specifically a diagnostic circuit capable of speedily detecting a failure of a plurality of function blocks connected to a bus.
2. Description of Related Art
Referring to FIG. 1, there is shown a block diagram of a conventional typical diagnostic circuit to which the present invention can be applied. Therefore, the prior art will be described with reference to FIG. 1.
In FIG. 1, Reference Numerals 1-A, . . . , 1-H designate function blocks A, . . . , H, respectively, and Reference Numerals 2-A, . . . , 2-H indicate bus drivers for reading out data in flipflops within the function blocks A, . . . , H, respectively. Furthermore, Reference Numeral 3 shows a controller for controlling a sequence of the diagnosis, and Reference Numeral 4 is indicative of a data memory for storing a correct value for the data in the flipflops within each of the function blocks in each diagnostic sequence. Reference Numeral 5 designates a comparison circuit for comparing the data in the flipflops within each function block with a corresponding correct value in the data memory 4, and Numeral 6 indicates a register for storing the result of the comparison in the comparison circuit 5 in each diagnostic sequence. Reference Numeral 7 shows a clock controller for generating a clock signal and a reset signal. The above mentioned circuits 1-A to 7 are interconnected as shown in FIG. 1.
FIG. 2 shows a circuit diagram of the function block 1-A in the prior art. Reference Numerals 1-A1, 1-A2, . . . , 1-An show a flipflop, and Reference Numeral 1-A-1 designates a NAND gate for supplying a clock to a register 1-A2. The other function blocks have a similar circuit construction.
FIG. 3 is a timing chart illustrating an operation of the conventional diagnostic circuit shown in FIG. 1 with each of the function blocks 1-A, . . . , 1-H being constructed as shown in FIG. 2.
The conventional diagnostic circuit operates in such a manner that, in order to diagnose the respective function blocks 1-A, . . . , 1-H at each time one operating clock or necessary clock is advanced, the result of the operation of the flipflops in the respective function blocks is sequentially read out for each of the function blocks, and the read-out result is compared with the previously prepared corresponding correct value. If the result of comparison is consistency, it is deemed as normality, and if the result is inconsistency, it is deemed as abnormality. This sequential operation is controlled by the diagnostic sequence controller 3.
For one purpose of shortening the diagnostic time in the above mentioned conventional method, Japanese Patent Application Laid-open Publication No. 63-174141 proposes that, in the case that there are a plurality of circuits having the same logic construction, the plurality of the logic circuits are caused to simultaneously perform the same operation, and on the other hand, there are provided a means for simultaneously reading out the flipflops and a means for mutually comparing a plurality of read-out results.
As already mentioned, the prior art has been such that the function circuits are tested and diagnosed by advancing the operating clock by one clock or a necessary number of clocks for completing one unitary functional operation, and by comparing the result of the operation of the flipflops within the function circuits with the expected value so as to know whether or not both are consistent. Thus, since the prior art is such that at each one clock or at each time the one unitary functional operation is completed, the reading-out and comparison of the results are performed, it is disadvantageous in that the testing and diagnosing time has become long in the case that since the function circuit is large, the function circuit is divided into a considerable number of function blocks from the viewpoint of restriction in the reading-out and comparison of the results.
It is also disadvantageous in that, in the case of comparing the result of the operation with the expected value after completion of a unitary function operation, the operation condition of the flipflop during a necessary number of clocks advanced until the completion of the unitary function operation is not necessarily certainly diagnosed.
Furthermore, there has not generally been made a countermeasure for shortening the diagnosis time for a function circuit which does not include a plurality of logic circuits of the same construction